FIG. 7 shows a circuit example of a five level inverter described in JP-T-2009-525717, which is a power converter circuit that converts from direct current to alternating current.
Direct current power supplies 60 and 61 (2Ed×2) are connected in series, and have a positive electrode potential P, a negative electrode potential N, and an intermediate point potential M. Generally, when configuring this direct current power supply from an alternating current power supply system, it is possible to configure by connecting an unshown rectifier and large capacity capacitor in series, or the like.
A one-phase (U-phase) circuit configuration (phase arm) Ua has an internal configuration with four semiconductor switches 51 and 54 are formed of IGBTs and diodes connected in series between the P side potential and N side potential. Two semiconductor switches 55 and 56 are formed of IGBTs and diodes connected in series between a connection point of the semiconductor switches 51 and 52 and a connection point of the semiconductor switches 53 and 54.
An anti-parallel circuit of IGBTs 57 and 58 is a bidirectional semiconductor switch connected between the M potential of the direct current power supply and a connection point of the semiconductor switches 55 and 56, and can be configured by connecting IGBTs (57 and 58) having reverse breakdown voltage in anti-parallel, as shown in FIG. 7, or by combining IGBTs (Q1, Q2) that do not have reverse breakdown voltage with diodes (D1, D2), as shown in FIG. 10A to 10C. FIG. 10A is a configuration wherein a series circuit of the IGBT Q1 and diode D1 and a series circuit of the IGBT Q2 and diode D2 are connected in anti-parallel. FIG. 10B is a configuration wherein the IGBT Q1 to which the diode D2 is connected in anti-parallel and the IGBT Q2 to which the diode D1 is connected in anti-parallel are connected in anti-series with a common collector, while FIG. 10C is a configuration wherein the IGBTs Q1 and Q2 are connected in anti-series with a common emitter. Apart from these configurations, there is a configuration using a diode bridge circuit and one IGBT, and the like.
A capacitor 59 is called a flying capacitor, has an average voltage across the capacitor 59 controlled to Ed, and an output of an intermediate potential Ed of the direct current power supply 2Ed realized by utilizing a charging and discharging phenomenon of the capacitor 59. These circuit groups Ua form one phase, and by connecting three units (Ua, Ub, and Uc) in parallel, a three-phase inverter circuit is configured.
An alternating current motor 62 is a load of the system. By adopting this circuit configuration, the potential of an alternating current output terminal of the converter is such that, by utilizing the P potential, N potential, and M potential of the direct current power supply, and a turning on and off of the semiconductor switches and the voltage of the capacitor 59, an intermediate potential of (P−Ed) and (N+Ed) can be output, because of which the five level output inverter is formed.
For example, five levels of voltage are output by operations whereby the IGBTs 51 and 52 are turned on when a voltage of 2Ed is output, the IGBTs 51 and 53 are turned on when a voltage of Ed is output, the IGBTs 58, 56, and 53 are turned on when a zero voltage (the M potential voltage) is output, the IGBTs 53, 55, and 57 are turned on when −Ed is output, the IGBTs 53 and 54 are turned on when −2Ed is output, and the like. There are also other operating patterns, but details will be omitted. Characteristics are that the voltage Ed, which is one-half of the direct current power supply 2Ed, is obtained by subtracting the voltage Ed of the capacitor 59 from the voltage 2Ed of the P side direct current power supply 60, and the voltage −Ed is obtained by subtracting the voltage (−Ed) of the capacitor 59 from the voltage (−2Ed) of the N side direct current power supply 61.
FIG. 13 shows a waveform example of an output line voltage (Vout). The waveform is configured of five levels of voltage and, as low-order harmonics are reduced and the switching loss of the semiconductor switches can be reduced in comparison with a two level type of inverter, construction of a highly efficient system is possible.
Also, FIG. 8 shows a circuit forming the basic form of a multilevel power converter circuit, such as the five level converter circuit of FIG. 7. As the numbers of parts with the same functions are the same as in the circuit of FIG. 7, a description will be omitted. A multilevel circuit can be realized by adding a converter circuit between terminals A and B in the drawing.
As an application circuit thereof, FIG. 9 shows a circuit example of a seven level inverter. This circuit is such that an alternating current output having seven levels of potential is possible by IGBTs 1 to 6 being connected as semiconductor switches between the positive electrode and negative electrode of a voltage (3Ed×2) of direct current power supplies 16 and 17 connected in series, a capacitor 13 charged to one unit of voltage (Ed) being connected between the collector of an IGBT 3 and the emitter of an IGBT 4, and a capacitor 14 charged to two units of voltage (2Ed) being connected between the collector of an IGBT 2 and the emitter of an IGBT 5.
Operations outputting a seven level voltage can be thought to be the same as in the case of five levels. For example, seven levels of voltage are output by operations whereby the IGBTs 1, 2, and 3 are turned on when a voltage of 3Ed is output, the IGBTs 1, 2, and 4 are turned on when a voltage of 2Ed is output, the IGBTs 1, 5, and 4 are turned on when a voltage of Ed is output, the IGBTs 1, 56, 5, and 4 are turned on when a zero voltage (the M potential voltage) is output, the IGBTs 4, 5, 55, and 11 are turned on when −Ed is output, the IGBTs 4, 2, 55, and 11 are turned on when −2Ed is output, the IGBTs 4, 5, and 6 are turned on when −3Ed is output, and the like. There are also other patterns, but details will be omitted. Characteristics are that the voltage Ed is obtained by subtracting the voltage 2Ed of the capacitor 14 from the voltage 3Ed of the P side direct current power supply 16, the voltage 2Ed is obtained by subtracting the voltage Ed of the capacitor 13 from the voltage 3Ed of the direct current power supply 16, the voltage −Ed is obtained by subtracting the voltage (−2Ed) of the capacitor 14 from the voltage (−3Ed) of the N side direct current power supply 17, and the voltage −2Ed is obtained by subtracting the voltage (−Ed) of the capacitor 13 from the voltage (−3Ed) of the N side direct current power supply 17.